This invention relates to the stacking of layers containing IC (semiconductor integrated circuit) chips, thereby obtaining high-density electronic circuitry. In general, the goal of the present invention is to combine high circuit density with reasonable cost. A unique aspect of this invention is that it provides a very low cost method of stacking commercially available IC's in TSOP's (thin small outline packages), while allowing the independent routing of several non-common I/O (input/output) signals from upper-level layers to the base of the stack. Cost reduction is accomplished by utilizing the relatively low cost leadframes and the ability to stack pre-packaged and pre-tested off-the-shelf IC's.
Most of the prior art disclosures describe methods of stacking multiple unpackaged IC chips. Oguchi et al. U.S. Pat. No. 5,332,922, Miyano et al. U.S. Pat. No. 5,440,171, and Choi et al. U.S. Pat. No. 5,677,569 disclose methods of stacking IC chips within a single package. Jeong et al. U.S. Pat. No. 5,744,827 discloses a new type of custom chip packaging which permits stacking, but which does not allow the use of off-the-shelf packaged IC's. Burns U.S. Pat. No. 5,484,959 shows a method of stacking TSOP packages which requires multiple leadframes attached above and below each TSOP and a system of vertical bus-bar interconnections, but which does not conveniently allow an expansion of the number of vertically interconnecting leads.